1. Field of the Invention
This invention relates to network communications, and, more particularly, to processing a frame-based or packet-based, with approximately periodic overhead, protocol.
2. Description of the Related Art
To accommodate increasing demand for bandwidth, optical networking has become more prevalent. Two well-known types of optical networks are Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH). Sometimes such networks are referred to as broadband networks, namely, networks capable of supporting interactive multimedia applications, as mentioned in “SONET” (Second Edition) by Walter J. Goralski (“Goralski”), at pages 20–23. As SONET and SDH have similar frame overhead configurations, for purposes of clarity, the remainder of this specification will tend to be disclosed in terms of a synchronous optical network using SONET. However, it will be appreciated by those of skill in the art, that this specification is equally applicable to other types of synchronous optical networks, including but not limited to SDH and other frame-based protocols having approximately periodic frames, and, more particular, fixed-length frames.
In SONET, a source network node sends a frame across a network link to a destination network node. In a SONET hierarchy, comprising a plurality of synchronous transport signal (STS) levels, each frame has rows and columns. For example, an STS-1 electrical level corresponding to optical carrier (OC) level 1 (OC-1) has a frame having 9 rows and 90 columns. For purposes of clarity, the remainder of this specification will tend to be disclosed in terms of an STS-1 frame. However, it will be apparent to those of skill in the art that this specification equally applies to STS-N levels, for N an integer conforming SONET standards.
STS-1 frames are transmitted at a rate of 8,000 frames per second, resulting in a data rate of 51.84 megabits-per-second (Mbps). Notably, frames may be concatenated to provide an envelope capable of a data rate in excess of 51.84 Mbps. Each frame comprises an envelope portion and an overhead portion. With respect to the overhead portion, each STS-1 frame transports Section Overhead (SOH) and Line Overhead (LOH) in the first three columns of a frame. SOH and LOH in combination are referred to as Transport Overhead (TOH). Another form of overhead in a frame is contained in an information payload area. This overhead is called Path Overhead (POH). POH is processed at SONET path terminating equipment as it travels as part of a Synchronous Payload Envelope (SPE). Thus, SPE comprises both user data and overhead, namely, POH. Section and line overhead is terminated at section and line terminating equipment.
Accordingly, it should be appreciated that a significant amount of channel space or, more particularly, informational space within a frame, is consumed by overhead. Furthermore, it should be understood that whether a channelized or non-channelized (“unchannelized”) approach to transporting multiple STS-1 frames is used, overhead increases linearly with respect to N, a number of STS-1 frame equivalents. For example, in a channelized architecture, such as STS-3, which illustratively may be thought of as three STS-1 frames stacked up upon one another, three STS-1 frames are processed per second as opposed to processing one STS-1 frame per second. In an unchannelized architecture, such as a super payload, STS-1 frames are concatenated to form STS-3c frames. In either architecture, processing overhead is substantial.
Heretofore, individual blocks of logic were used to support each function for each element of overhead. Massive parallelism for processing each byte was used for immediacy. Such conventional configurations used flip-flops for storing information for such processing. Thus, it should be understood that integrated circuits configured to implement individual logic blocks for processing each overhead element or byte type result in a significant number of transistors or gates. Accordingly, integrated circuits or microchips constructed with such individual blocks of logic consumed significant amounts of area on a semiconductor wafer (“semiconductor wafer real estate”). Moreover, more gates translate into more power consumption.
Accordingly, it would be desirable to provide a device for processing overhead that consumes less semiconductor wafer area and less power.